1. Field of the Invention
The present invention generally relates to techniques for improving program performance on computing devices. More specifically, the present invention relates to techniques that improve program performance by enregistering memory locations using additional registers.
2. Related Art
Binary translation techniques facilitate translating object code targeted for one hardware implementation to execute on another hardware implementation. For instance, such techniques facilitate translating a binary generated for one instruction set architecture (ISA) to a second ISA. While binary translation may involve significant overhead, it allows applications to be run transparently across different architectures without recompilation. Such techniques can simplify distributing program code across a wide range of architectures, and can be extremely useful when access to program source code is restricted.
Note, however, that a compiler typically generates object code to match the feature set of an intended target architecture. For instance, a compiler typically generates code which is optimized for the given number of registers available in the intended target architecture. Note that re-optimizing existing object code to take advantage of the different characteristics of a new target architecture is a complicated process which is typically not performed during binary translation. Hence, binary translation typically does not take full advantage of the resources available in the new target architecture. For instance, when a new target architecture includes more registers than the original intended target architecture, such additional registers may be left unused.
Hence, what is needed is a method that performs binary translation without the above-described limitations of existing techniques.